

module test_io(
    CLK1,
    dat
);
    input wire CLK1;
    output wire[4:0] dat;
    def_clk clk(CLK1,clk_in);


    reg[15:0] counter = 16'd0;
    assign dat[0] = counter[0];
    assign dat[1] = CLK1;
    assign dat[2] = counter[2];
    assign dat[3] = counter[3];
    

    always @(posedge clk_in) begin
        counter <= counter + 16'd1;
    end
    

endmodule